1. Field of the Invention
The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus for processing electronic image data captured via an optical system.
2. Description of the Related Art
In general, in an electronic image pickup device, such as a digital camera, a subject image formed via an optical system is photoelectrically converted by an image pickup element, such as, a CCD, image pickup data is obtained, and the image pickup data is subjected to various image processing. Thereafter, generally, the image is compressed by JPEG compression format or the like, and is recorded to a recording medium, such as a memory card. The electronic image pickup device, such as a digital camera, has a common function of an image processing apparatus.
FIG. 32 is a diagram showing the general image-processing procedure in the image-processing apparatus.
An image pickup device, such as a CCD, photoelectrically converts an optical subject image which is formed by an optical system and generates an electrical image pickup signal. The image pickup signal is subjected to pre-processing, such as correction of pixel defect or A/D conversion and is thereafter stored in a frame memory.
Subsequently, image data stored in a frame memory is read and is subjected to various image processing including processing converting from a single-chip signal into a three-chip signal, low-pass filter processing, edge emphasis processing, and enlarging and reducing processing, through a first image process, a second image process, . . . , and an N-th image process.
An image signal after the image processing is compressed by JPEG compression format, and is recorded to a memory card, as an image file.
FIG. 33 is a block diagram showing the configuration of a conventional image processing apparatus for the general image processing shown in FIG. 32.
The image processing apparatus comprises: a CCD 91; a pre-processing unit 92; a frame memory 94; a first image-processing unit 95a; a second image-processing unit 95b; . . . ; an N-th image-processing unit 95n; a JPEG processing unit 96; a memory card 97; a bus 98 that connects the circuits except for the CCD 91 to a CPU 93, which will be described later; and the CPU 93 that entirely controls the image processing apparatus and includes the above-described circuits.
The image processing apparatus with the above-described configuration shown in FIG. 33 has a specific procedure as follows to perform the processing as shown in FIG. 32.
First, the image data from the pre-processing unit 92 is temporarily stored in the frame memory 94 via the bus 98.
Subsequently, the image data is read from the frame memory 94, is inputted to the first image processing unit 95a via the bus 98, and is subjected to the first image processing. The image data after the processing is written to the frame memory 94.
Similarly, the image data after the first image processing is read from the frame memory 94, is inputted to the second image processing unit 95b via the bus 98, and is subjected to the second image processing. The image data after the second processing is written to the frame memory 94. The same processing is repeated every image processing unit.
As mentioned above, in the image processing, the image data flows to the bus 98 many times. Since image data generally has a large data size, a load is imposed on the bus 98. The large load to the bus 98 is more serious in the use of continuous image pickup operation.
In the view of the foregoing, Japanese Unexamined Patent Application Publication No. 2000-311241 discloses a technology, by which a plurality of image processing units are connected for pipeline processing and images from a frame memory are subjected to the pipeline processing, thereby suppressing the bus's load. Thus, the bus's load is suppressed and the image processing including enlarging and reducing processing is performed in real time without increasing the memory capacity.
Further, Japanese Unexamined Patent Application Publication No. 2000-312327 discloses a technology, by which images stored in a frame memory are read in units of a block in a predetermined direction (column direction), thereby reducing the amount of buffer in the pipeline processing. Thus, an image processing apparatus with low power-consumption and memory-saving is configured.
In a camera optical system including a digital camera or a silver-halide camera, although varied, a distortion aberration is generally caused. In the case of capturing an image of a lattice subject, the distortion aberration is observed as a barrel image or pincushion image (refer to FIGS. 3A to 3C according to a first embodiment of the present invention). Currently-sold cameras have many types of optical zoom operation. With the zoom optical system, the focus distance is changed within a zoom range from the wide end to the tele-end and then the state of the distortion aberration changes in many cases.
In order to solve the phenomenon, Japanese Unexamined Patent Application Publication No. 6-181530 discloses one technology that is conventionally developed to correct the distortion, as a part of image processing. In the normal image processing as disclosed in Japanese Unexamined Patent Application Publication No. 6-181530, data is read in units of a line from a frame memory.
Further, Japanese Unexamined Patent Application Publication No. 10-224695 discloses as another technology for correcting the distortion as a part of image processing, wherein each image processing unit randomly accesses a frame memory. With the technology, since the image processing unit does not have a buffer, advantageously, the circuit scale of image processing unit is reduced.
Further, in the camera optical system, it is well-known that a chromatic aberration is caused. The chromatic aberration is caused because the refractive index is varied depending on the wavelength of light when light is incident on the optical system. In the case of forming an optical image through the optical system, the chromatic aberration appears, as a phenomenon of slight shift of optical images formed every wavelength. The optical system is designed such that the chromatic aberration is suppressed as much as possible. However, all the chromatic aberrations are not removed in view of arrangement space, weight, and costs.
As disclosed in Japanese Unexamined Patent Application Publication No. 6-181530, in order to perform a correction processing of the distortion of one line of corrected image, referring to FIG. 34, a plurality of lines necessary for distortion correction of the image data before the correction needs to be read throughout the width in the lateral direction of the entire image. FIG. 34 is a diagram for explaining the amount of memory necessary for conventional distortion correction processing. The image data of the plurality of lines is temporarily stored in the buffer arranged in the image processing unit, and is processed. Therefore, the buffer needs a relatively large capacity to obtain the corrected image of one line, the circuit scale increases, manufacturing costs increase, and the power consumption raises. Further, the processable image size is limited, depending on the capacity of buffer memory in the image processing unit.
Further, as disclosed in Japanese Unexamined Patent Application Publication No. 10-224695, the frame memory comprising an SDRAM and the like is randomly accessed and then the data transfer time increases the entire processing time, as compared with the burst transfer for reading operation from the SDRAM.
The image processing apparatus comprises both a processing block for the above-described distortion correction processing and a processing block for enlarging and reducing processing, thereby enabling both the enlarging and reducing processing and the distortion correction processing. However, both the processings need interpolation and calculation every pixel and the processing circuit has a large scale. Thus, mere adoption of the configuration having both the processing circuits increases the circuit scale. Further, the power consumption increases and the manufacturing costs raise.
Preferably, the above-described chromatic aberration is corrected without increasing the costs.
The present invention is devised in consideration of the above circumferences, and it is one object of the present invention to provide an image processing apparatus for image processing without increasing the amount of data transfer of bus and the memory capacity.
Further, it is another object of the present invention to provide an image processing apparatus having a small circuit scale for both the enlarging and reducing processing and the distortion correction processing with low power-consumption.
Furthermore, it is another object of the present invention to provide an image processing apparatus having a small circuit scale for both the correction of distortion and the correction of chromatic aberration with low power-consumption.